Understanding uboot code with Bare metal drivers using Xilinx FPGA board

This session represents, Bare metal drivers debug on FPGA board starting with Startup code & different controllers(Interrupt Controller,Timer,UART,QSPI) present onboard.
This session describes in detail of controller
Setup,Init,Functionality,Stop,&Shutdown procedure.
This session is useful to understand the FSBL u-boot code (First stage boot loader) in the form of Bare metal drivers & so it is useful in debugging u-boot code in a granular level.
SoC: Xilinx Zynq Zc702 (ARM Cortex A9 Dual core)
Board used: Xilinx FPGA Board (ZED Board)