oreboot 2022 status report - on to RISC-V

This year we pivoted the oreboot project, a downstream fork of coreboot
written entirely in Rust, to focus on RISC-V platforms, including the first
version of Beagle-V. We have focused our energies on platforms we can control from power-on reset, with no binary blobs.

Over the last year, the Allwinner D1 SoC, which offers a Linux-capable 64bit
XuanTie C906 RISC-V core and is found on many boards, has been fully ported,
including DRAM init. In addition, we picked up the work on the JH7100 SoC again
that was found on the BeagleV Starlight SBC, because it is also on the StarFive
VisionFive board, which has been provided to us by RISC-V International for the
developer support program.

In this talk, we present challenges we faced during
the development, including writing DRAM code from C code, not chipset documentation;
how we are taking advantage of the rapid growth of "bare metal" support in the Rust ecosystem and
how it has impacted our code, in ways large and small; and how the project is growing as new members
join.

Finally, we summarize the current status of the oreboot project.